Abstract: In this paper, a high-performance adder is designed for low power application. Carry Select Adder (CSLA) is known to be the fastest adder among ...
Missing: published | Show results with:published
Optimization of Area and Power. Consumption In Carry Select Adder By. Using BEC. N. Mageshwari, N. Sasipriya, R. Ramya. As-Salam College of. Engineering and.
To overcome this problem an add-one circuit was introduced by incorporating a BEC. Therefore in Modified Linear. CSLA, a Binary to Excess-1 circuit is used.
This paper proposes an efficient method which replaces the BEC using D latch. Experimental analysis shows that the proposed architecture achieves the three ...
Missing: published IJARIIT
In [1]. RCA was replaced with Binary to Excess-1 Converter. (BEC) in CSA to reduce power and area. This design reduced the power but the delay was found to be ...
The gate level modification is to reduce the power and area of carry select adder by using the concept of Arithmetic Logic Unit (ALU). In this paper , different ...
This paper presents performanceanalysis of different Fast Adders. The comparison is done on thebasis of three performance parameters i.e. Area, Speed andPower ...
Missing: published IJARIIT
The study presents a new dynamic logic named sp-D3L that overcomes the speed limitations of D3L. Power consumption is significantly reduced by using the sp-D3L ...
A novel high-speed and area-efficient adder architecture based on a carry-select adder and Han-Carlson adder that achieves the lowest ADP and PDP.
Missing: IJARIIT | Show results with:IJARIIT
Oct 17, 2018 · PDF | On Oct 17, 2013, Gowtham Palanirajan published DESIGN OF CARRY SELECT ADDER WITH AREA AND POWER EFFICIENCY | Find, read and cite all ...
Missing: Optimization published IJARIIT