Abstract: In this paper, a high-performance adder is designed for low power application. Carry Select Adder (CSLA) is known to be the fastest adder among ...
Missing: published | Show results with:published
By using the BEC based on CSLA architecture, the area delay product. (ADP) is high. The proposed CSLA is being designed by Pass transistor logic (PTL) technique ...
Missing: Optimization published IJARIIT
A digital designer has to concentrate on many criteria like. Circuit speed, power consumption, area, and cost. The fundamental arithmetic operations like ...
Missing: Optimization BEC
This paper presents performanceanalysis of different Fast Adders. The comparison is done on thebasis of three performance parameters i.e. Area, Speed andPower ...
Missing: published IJARIIT
Oct 7, 2019 · ... BEC-based structure reduces logic redundancy, thus reducing area and power consumption. ... optimization compared with regular CSLA. In ...
Missing: IJARIIT | Show results with:IJARIIT
A novel high-speed and area-efficient adder architecture based on a carry-select adder and Han-Carlson adder that achieves the lowest ADP and PDP.
Missing: IJARIIT | Show results with:IJARIIT
The basic idea of this work is to use Binary to Excess-1. Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption..
Missing: Optimization published IJARIIT
In [1]. RCA was replaced with Binary to Excess-1 Converter. (BEC) in CSA to reduce power and area. This design reduced the power but the delay was found to be ...
Due to this, HanCarlson adder can achieve similar speed performance as that of Kogge-Stone adder, at lower power consumption with area. Therefore it is ...
FORWARD. On behalf of the 1st National Executive Council of Academia in Information Technology Profession (AITP): an umbrella body of all academia in ...