WO2010039871A1 - Reconfigurable array of magnetic automata (rama) and related methods thereof - Google Patents

Abstract

A method and apparatus of constructing magnetic automata and related structures through the development of a self-assembled thin film array of magnetic nano-pillars. The method and apparatus provides the ability to configure patterns electrically on a device without all requirements of producing a complicated pattern on a semiconductor chip. This relieves, for example, the requirement for using very expensive lithographic tools in the fabrication of these structures. Provided is an architecture made from a self assembled thin film array of magnetic nano-pillars in a cross bar array that not only performs logic operations but also stores information.

Description

Reconfigurable Array of Magnetic Automata (RAMA) and Related Methods thereof

RELATED APPLICATIONS The present application claims priority from U.S. Provisional Application Serial No.

61/101,470, filed September 30, 2008, entitled "Method and System for Reconfigurable Array Magnetic Automata (RAMA);" the disclosure of which is hereby incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

Complementary metal-oxide-semiconductor (CMOS) is the current standard for logic circuitry, and although it is a remarkable technology, it is projected to survive only another ten to twenty years because of its inability to scale to dimensions below about 10 nm. At the current rate of scaling of transistor count, CMOS below about 10 nm would dissipate too much heat to be practical, and thus the end of the Moore's Law roadmap is in sight. A technology capable of dissipating orders of magnitude lower power than CMOS at the same scale and could be the holy grail of the computing industry — the replacement for CMOS.

BRIEF SUMMARY OF THE INVENTION

An aspect of an embodiment provides, but not limited thereto, a method of constructing magnetic automata and related structures through the development of a self- assembled thin film array of magnetic nano-pillars. For instance, it provides the ability to configure patterns electrically on a device without all requirements of producing a complicated pattern on a semiconductor chip. This relieves the requirement for using very expensive lithographic tools in the fabrication of these structures.

An aspect of an embodiment provides an architecture made from a self assembled thin film array of magnetic nano-pillars in a cross bar array that not only performs logic operations but also stores information. This technology goes significantly beyond these early ideas where complicated arrays had to be fashioned lithographically. In the case of an embodiment of the Reconfigurable Array Magnetic Automat (RAMA); the magnetic bits may be regular arrays that are amenable to various self assembly schemes and each magnetic pillar can be individually addressed and controlled using electric fields (i.e., rather than charge currents or passing currents, for instance). The magnetism in the dots can be gated and clocked electrically without having to strongly varying magnetic fields or large electrical currents, thereby allows these circuits to operate at very low power and to scale to dimensions not feasible with CMOS .

An aspect of an embodiment provides the ability to overcome ultimate CMOS limitations by using a Reconfigurable Array Magnetic Automata (RAMA) for performing logic operation and storing information.

An embodiment for a method of constructing a thin film array of nano-pillars may involve in-part brute force lithography. (See examples of lithography as is established in U.S. Patents Nos. 6,178,112 and 7,119,410.)

An aspect of an embodiment, allows for, but not limited thereto, the memory cell to be much smaller than the existing prior art. For example, see the distance between the wires as is shown in U.S. Patent No. 5,343, 422. Regarding an embodiment, the pillars 5 may range in diameter size (edge to edge of the pillars) from between about 3 nm to about 25 nm. In an embodiment, the pillars 5 may be less than about 15 nm at the limits of CMOS. It should be appreciated that the pillar diameter may be less than about 3 nm or greater than about 25 nm.

In an embodiment, the spacing between the pillars 5 (edge to edge of the pillars) may be of the same order as the pillar diameter (but not necessarily). For example, if the pillars have a diameter of about 10 nm then the pillars may be separated by about IOnm. It should be appreciated that the pillar spacing may be less than about 3 nm or greater than about 25 nm; range between from about 3 nm to about 25 nm. The spacing will determine, among other things, the coupling between the pillars (ferromagnetic or antiferromagentic). In an embodiment, the width of the wires above and wires below the pillars may be slightly larger than the diameters of the pillars (but not necessarily). For example, pillars having a diameter of about 10 nm may have wires of about 14 nm wide and they would be separated by about 6nm. It should be appreciated that other ratios of comparative sizes involving diameters, widths and separations may be selected as desired or required and shall be considered within the context of the invention.

It should be appreciated that the diameters of the pillars, separation between the pillars, and width of the wires may have various widths, lengths, distances, sizes, contours, and shapes as desired or required and is considered to be within the context of the embodiments. Moreover, their relative widths, lengths, distances, sizes, contours, and shapes of any of the elements relative to any adjacent, proximal or related elements may vary as well.

It should be appreciated that the wafers, substrates, various layers discussed herein, connections, vias, conductors, and junctions may have various widths, lengths, distances, sizes, contours, and shapes as desired or required and is considered to be within the context of the invention.

In an embodiment, the reconfϊgurable magnetic automata is constructed by combining three layers. It should be appreciated that more layers may be added if desired or required. The top layer may comprise wires or conducting material running at least substantially parallel to one another separated by an insulating material, all of which run at least substantially horizontally. The middle layer may include a random array of up and down polarized ferromagnetic (FM) pillars embedded in a ferroelectric (FE) or piezoelectric (PE) matrix. The nanopillars may be covered with either a novel oxide that exhibits very large changes of dielectric constant with application of magnetic field or an insulator that can act as a tunnel barrier. The third and bottom layer may comprise of wires or conductors also running in a horizontal direction, but at least substantially perpendicular to the wires and conductors of the top layer. In between these wires or conductors on the third layer is an insulating material. A substrate is contained under this third and bottom layer. Of course the substrate may be employed on the top layer instead of the bottom layer or in addition to the bottom layer; thus, the structure may be fabricated using a flip-chip approach, for example, that would bond two substrates together. Any vias, junctions, leads, connections, transistors or circuits may be employed to communicate among all these various components or elements as desired or required and is considered to be within the context of the invention. In an embodiment, constructing nano-pillar structures uses an advanced and novel method known as block co-polymer patterning. It can also be constructed using lithographic techniques such as e-bean lithography, polymeric self assembly, or damaged template growth. For polymeric self assembly and block co-polymer patterning see, for example: S. Ren, R. Briber and M. Wuttig. Diblock copolymer based self assembled nanomagnetoelectric, Appl. Phys. Letters 93, 173507 (2008); and I. Bita, Joel K.W. Yang, Y. S. Jung, C. A. Ross, E. L. Thomas, K. K. Berggren, Graphoepitaxy of self-assembled block copolymers on 2D periodic patterned templates, Science 321 (5821) p939-943 (2008). For damaged template growth, see for example J.L. Gray, S. Atha, R. Hull, and J.A. Flora, "Hierarchical Self- Assembly of Epitaxial Semiconductor Nanostructures", Nanoletters 4 2447 - 2450 (2004).

Various embodiments may use methods for writing bits to the nano-pillar memory cell, which take advantage of the antiferromagnetic coupling of the nanopillars. Furthermore, various additional methods can be used to read the memory cells constructed from the magnetic nanopillars. The output bits can be read out magnetoresitively as well as capacitively.

An aspect of an embodiment provides a thin film array of magnetic nano-pillars as disclosed herein that may be used in, but not limited thereto, microprocessors, microcontrollers, static RAM, and other digital logic circuits and memory circuits both embedded with the logic circuits or stand alone.

An aspect of an embodiment provides a thin film array of magnetic nano-pillars as disclosed herein that may be used in, but not limited thereto, for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for many and various types of communication.

An aspect of an embodiment of the present invention includes the thin film array of magnetic nano-pillars as disclosed herein as a medium, device or system, the associated method of fabricating the same, the system, processor or computer for use therewith, and the apparatus or equipment utilized for fabricating the same. An aspect of an embodiment provides self assembly techniques (for example, defect templated growth or patterning by block co-polymers) to prepare ordered arrays of the various structures discussed herein, including multilayered structures with perpendicular anisotropy in the unstrained condition, in which the ferromagnetic nanopillars may be arranged so that they couple antiferromagnetically. For instance, a magnetic rotation is caused by the piezoelectric strain coupling or ferroelectric strain coupling from the surrounding matrix of the nanopillars.

An aspect of an embodiment or partial embodiment (or combinations of various embodiments in whole or in part) comprises, but not limited thereto, a non-volatile reconfigurable array of modifiable automata (RAMA) device. The device may comprise: an array of nanopillars functionally addressable by conducting elements that provide a control electric field to the nanopillars; and whereby the array of nanopillars may comprise at least one material whose properties can be controlled by the control electric field. In an embodiment, the nanopillar properties may be the direction of magnetization of the material of at least one of the nanopillars of the nanopillar array. In an embodiment, the nanopillar properties may be the direction of polarization of the material of at least one of the nanopillars of the nanopillar array.

An aspect of an embodiment or partial embodiment (or combinations of various embodiments in whole or in part) comprises, but not limited thereto, a device comprising a non- volatile array of magnetic nanopillars, wherein the nanopillars may have been previously written at some prior time. The nanopillar may be a ferromagnetic (FM) material. The device may comprise a layer for the array of nanopillars located above or below the array of nanopillars. The nanopillar layer may comprise a colossal magnetocapacative (CMC) material. Further, the device may be configured whereby if a global magnetic field is applied to the array of nanopillars (for example, in a direction at least substantially parallel to the nanopillars), then the magnetic field on the CMC material of the nanopillar layering is subject to the sum of the fields produced by the magnetic moments of the nanopillars and the applied global magnetic field, and wherein the capacitance of the dielectric constant of the CMC material is capable of being read.

An aspect of an embodiment or partial embodiment (or combinations of various embodiments in whole or in part) comprises, but not limited thereto, a device comprising a non- volatile array of magnetic nanopillars, wherein the nanopillars may have been previously written at some prior time. The nanopillar may comprise a ferromagnetic (FM) material. The device may have a layer for the array of nanopillars located above or below the array of nanopillars, and the nanopillar layer may comprises a magnetoresistive oxide material. The device may be configured whereby if a global magnetic field is applied to the array of nanopillars (for example, in a direction at least substantially parallel to the nanopillars) and a current is passed through the nanopillars and the nanopillar layer, then the resistance on the magnetoresistive oxide material of the nanopillar layering changes, and wherein the resistance of the magnetoresistive oxide material is capable of being read.

An aspect of an embodiment or partial embodiment (or combinations of various embodiments in whole or in part) comprises, but not limited thereto, a device comprising a non- volatile array of magnetic nanopillars, wherein the nanopillars may have been previously written at some prior time. The nanopillar may comprise a ferroelectric (FE) material. The device may comprise: a layer for the array of nanopillars located above or below the array of nanopillars. The nanopillar layer may comprise a paraelectric material. The device may be configured whereby if an electric field is applied to the nanopillars, then the electric field on the paraelectric material of the nanopillar layering is sensitive to the total electric field due to the ferroelectric (FE) material of the nanopillars and the applied electric field, and wherein the capacitance of the dielectric constant of the paraelectric material is capable of being read.

These and other objects, along with advantages and features of various aspects of embodiments of the invention disclosed herein, will be made more apparent from the description, drawings and claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated into and form a part of the instant specification, illustrate several aspects and embodiments of the present invention and, together with the description herein, serve to explain the principles of the invention. The drawings are provided only for the purpose of illustrating select embodiments of the invention and are not to be construed as limiting the invention. Figure 1 provides an exploded schematic perspective view of an array of an embodiment.

Figure 2 provides an enlarged cross-section of an exploded schematic view of a partial segment of the array shown in Figure 1.

Figure 3(A) provide a schematic cross-section perspective view of a nanopillar pair with no applied electric field.

Figure 3(B) provides a schematic cross-section perspective view of a nanopillar with an applied electric field.

Figure 4(A) is a schematic view of a bit formed by four nanopillars of an embodiment providing a "0" or unwritten state. Figure 4(B) is a schematic plan view of a bit formed by four nanopillars of an embodiment providing 1" bit or written state.

Figure 5(A) provides a schematic plan view of an example of an array configured as a "NOR" gate of an embodiment.

Figure 5(B) provides a schematic plan view of an example of an array configured as a "NOT" gate of an embodiment. Figures 6(A)-(B) provides a schematic perspective view illustrating the writing function to a portion of an array of an embodiment.

Figure 7 provides a schematic perspective view illustrating the reading function (reading capacitively) of a portion of an array of an embodiment. Figure 8 provides a schematic plan view of an array 25 (partial array as shown) with groupings of nine nano pillars in their respective bit. Figure 9(A) provides an exploded schematic perspective view of an array of an exemplary embodiment of the RAMA system.

Figures 9(B)-(C) provide schematic perspective view of examples of coils associated with the RAMA system of Figure 9(A) .

Figure 10 provides a cross-section of an exploded schematic view of a partial segment of an array an embodiment.

Figure 11 provides a cross-section of an exploded schematic view of a partial segment of an array an embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Turning now to the drawings, three layers of an embodiment are shown in Figure 1. Figure 1 provides an exploded schematic perspective view of an array 25 with a top layer 1 (or may be multiple layers as desired or required) including wires 2 that are made of conducting material running at least substantially parallel to each other, in a lateral direction (as shown) or longitudinal direction, whichever direction is perpendicular to the bottom wires or conducters 8 of the bottom layer 7 (or may be multiple layers as desired or required) of the array 25. As shown, the bottom wires or conductors 8 are running longitudinally and the top wires or conductors 2 are running laterally (however, it should be appreciated that they may be running longitudinally if bottom conductors 8 are running laterally). In between each of the top wires or conductors 2 is to be an insulator 3 (or multiple layers) running along the wires or conductors. In between each of the bottom wires or conductors 8 is to be an insulator 9 running along the wires or conductors. It should be appreciated that lateral and longitudinal directions are intended for illustrative purposes and actual alignments may vary.

Briefly referring to Figure 2, there is illustrated an enlarged cross-section of an exploded schematic view of a partial segment of the array 25 shown in Figure 1 that represents an exemplary embodiment. This cross-section view represents the array 25 having a top layer 1, middle layer 4, and bottom layer 7 — and its associated components (as will be discussed herein) sliced longitudinally 11 (as referenced in Figure 1). It should be appreciated that middle simply means interposed or between the layers. It does not necessarily mean it must be at an exact center, i.e., at equal distances. Still referring to Figures 1-2, the middle layer 4 may contain a random array of nanopillar structures 5 which may be embedded in a ferroelectric (FE) or piezoelectric (PE) matrix 6 such as BiFeO3, SrTiO₃, SrBaTiO₃ PZT, PZN, etc. The random array of up and down polarized ferromagnetic (FM) pillars (such as CoFeO4, FE3O4 or other strongly ferromagnetic oxide that is ferromagnetic to temperatures well above ambient temperature) embedded in a ferroelectric (FE) or piezoelectric (PE) matrix (such as BiFeO₃) can have their magnetizations rotated from being perpendicular to either top or bottom surface of the nanopillar 5 to being in the plane of the magnetic memory cell with any application of a modest electric field. Further, as well be discussed later, an aspect of an embodiment may have pairs of nanopillars that are coupled antiferromagnetically. For instance, but not limited thereto, an embodiment is capable of pairing the nanopillars into groups of four to create a bit (other pairings of nanopillars and numbers in a group may vary as desired or required for operational and manufacturing purposes).

The bottom layer 7 may include a set of bottom wires or conductors 8 running horizontally in a direction either laterally or longitudinally, as defined above, in a direction perpendicular to those of the wires or conductors 2 of the top layer 1. In between the wires 8 is an insulator 9 which runs across the length of the wires and serves as a shield between the wires 8. The bottom layer 7 may be similar to the top layer 1 except that the bottom wires or conductors 8 run in a direction perpendicular to the top wires or conductors 2. In addition to the difference between the direction of the wires, the bottom layer 7 may include the addition of a substrate 10 located under the bottom wires or conductors 8 and insulators 9. It should be appreciated that in other embodiments an additional substrate may be located on top of the wires 2 and insulators 3; or simply a top substrate my exist and forego the bottom substrate. As shown in Figure 2, a nanopillar layer may 11 be disposed on or in communication with (directly or indirectly) the nanopillar structures 5. The nanopillar layer 11, for example, may be made from one of many material choices as discussed herein, or other material as desired or required. It should be appreciated that a nanopillar structure 5 may be made up of more than one material. In an embodiment, the nanopillar layer 11 may be made with a novel oxide that exhibits very large changes of dielectric constant with the field or exhibits large changes in capacitance. This material is labeled in Figure 2 as a colossal magnetocapacitive (CMC) material, such as LaPrCaMnO₃, LaSrMnO₃ or other manganite because such a capacitor built of this compound can exhibit large changes in capacitance with changes in magnetic field. While the nanopillar layer 11 as shown is illustrated as a colossal magnetocapactive (CMC) material, there is another possibility for the nanopillar layer 11. The other possible material that can make up the nanopillar layer 11 above (or below) the nanopillar 5 is an insulator that can act as a tunnel barrier. In either approach (CMC or insulator as a tunnel barrier), these ferromagnetic nanopillars 5 are arranged so that they couple antiferromagnetically. The nanopillar structure 5 may be ferromagnetic layer (FM), or other material as desired or required. For instance, it is possible to use other ferromagnetic compounds that have perpendicular anisotropy.

As illustrated the CMC layer or segment is deposited solely over or in communication solely with the nanopillars itself, however it should be appreciated that it may be deposited over or in communication with the entire matrix , or some combination or variation thereof.

Figures 3(A) and 3(B) illustrate a schematic perspective view of the various exemplary positions of the magnetic field in the ferromagnetic nanopillars 5. As shown in Figure 3(A), when there is no electric field applied to the nanopillar 5, the magnetic field 12, 13 (referenced as M) of each pair of nanopillars 5 is opposite with one another or antiferromagnetic. One magnetic field will be pointed in the "up" direction 12 while one will be pointed in the "down" direction 13. The "up" direction, in terms of Figure 1 is the direction perpendicular (i.e., vertical) from the middle layer 4 and pointing towards the top layer 1. The "down" direction, in terms of Figure 1 is pointing in a direction perpendicular (i.e., vertical) to the middle layer 4 and towards the bottom layer 8, directly opposite of the direction of "up". As shown in Figure 3(B), when an electric field is applied to a nanopillar 5, the magnetic field 14 in the nanopillar 5 is pointed the direction of "in-plane" with the middle layer (i.e., horizontal). The direction of "in-plane" is to be defined as parallel to that of the middle layer 4, in a direction perpendicular to that of "up" or "down".

As indicated in Figures 4(A)-(B), to create a bit (referenced as either 15 or 16), four nanopillars 5 are arranged in a square, with corners polarized in the "up" direction 12 (illustrated in white color dot) and opposite corners polarized in the "down" direction 13 (illustrated as black color dot). Referring to Figure 4A, to create a "0" or unwritten state 15, the top left and bottom right corner of the four nanopillar square are to be in the "up" direction 12 (white) while the top right and bottom left corner nanopillars are in the "down" direction 13 (black). Referring to Figure 4B, to create a "1" bit or written state 16, the top left and bottom right corner nanopillars of the four nanopillar square are to be magnetized in the "down" direction 13 while the top right and bottom left corner nanopillars are in the "up" direction 12. Thus, an aspect of an embodiment may be applied so that the ferromagnetic nanopillars 5 couple antiferromagntically. This would be done through their dipolar exchange. Doing this creates two stable configurations of the array 25 in which each adjacent nanonpillar is oppositely magnetized for each configuration as desired or required. In an embodiment, a bit would consist of four nanopillars in a square (or other geometric configuration as desired or required) to provide a symmetrical arrangement with two corners to be polarized up and down, as for example shown in Figure 4.

The two states of the bit could be represented by the state of the left uppermost corner which could be up or down and the other adjacent nanopillars (and their associated antiferromagentic coupling (i.e., state)) would adjust accordingly due to their antiferromagnetic nature. Any pattern of such bits could be formed in the array by applying electric fields to any nanopillars that need to be removed from those active in the gates. This removal would correspond to the magnetizations being shifted to being "in-plane" from being either "up" or "down".

It should be appreciated that there are other possible arrangements of bits and nanopillars of the array 25. Referring to Figure 8, for example but not limited thereto, an array 25 (partial array as shown) with groupings of nine nano pillars 5 in a respective bit 41 may be realized in two types of bits. One type consisting of the nano pillars 5 on the outside corners (as shown with dashed-lines surrounding the nanopillars for illustrative purposes) in a square arrangement or a second type having a square consisting of the nanopillars 5 in between the corner pillars in a 45 degree arrangement (angle alignment illustrated using the dotted lines). For instance, but not necessarily, the center pillar is not used and is always deactivated for both arrangements. The arrangement of nanopillars in between, the corner pillars are at 45 degrees to the first arrangement. Using these two types of arrays, crossovers in the same plane can be realized. The logic or memory of the two types of bits can be obtained or accessed by propagating the bits in two different directions as shown, for example, by the arrows designated as "PD." Please note that to be able to deactivate the appropriate pillars in each of the nine pillar arrays additional wires and control circuitry may be required. Also, columns and rows of nanopillars 5 may be provided between adjacent bits 41 to provide the required symmetrical spacing of the bits so the appropriate coupling is maintained throughout the array.

While Figure 4 provides, for example, a bit formed by four nanopillars, it should be appreciated that for memory, in an embodiment each nano-pillar can be a bit. It is envisioned within the context of the invention a structure with an additional gate between the pillars that can be used to control the interaction between the bits. The interaction between the bits can be made either ferromagnetic or antiferromagnetic depending on the electric field on this additional gate. In this case each pillar can be a bit. Such an approach would involve controlling the dipolar exchange between the bits. Making this embodiment of the array will be more difficult and it would have to be clocked, it would not operate autonomously or semiautonomously. Writing

Writing to the array or portions of the array may be accomplished using a variety techniques regarding the various embodiments. As shown in Figures 6(A), in one method, writing can be done by first applying an electric field (for example the bias as indicated by "+" and "-" symbols) to put the magnetization, and hence the magnetic field 14 in the nanopillar to the "in-plane" direction (i.e., horizontal). More specifically, the electric field acts on the interface between the FM nanopillars 5 and the PE or FE matrix 6. This is a reason why the width of the conducting lines 2, 8 may be somewhat larger than the diameter of the nanopillars 5 so that the electric field extends a short distance into the matrix 6. In turn, this provides the strain which causes the magnetization of the nanopillars to rotate in- plane. A small magnetic bias field 19 is applied in a direction either up or down to accomplish the desired writing. If a 0 bit is a desired then the magnetic bias field is in the up direction and if a 1 bit is desired then the magnetic bias field 19 is in the down direction (i.e., apply the small magnetic bias field 19 in the direction that the writing is desired). The electric field is then removed (as shown in Figure 6(B) and the input is written to the magnetic nanopillar 5 as was determined by the aforementioned magnetic bias field (i.e., remove the electric field and the input has been written). As shown in Figure 6(B), the nanopillar magnetic field is polarized in the "up" direction 12. Another method for writing to the logic array (not shown) is to deactivate all of the elements (i.e., nanopillars) that form the "input" bits and to apply a small magnetic bias field in the "up" direction. After the small magnetic bias field is applied in the "up" direction, the inputs that need to be in the "up" direction are selectively activated. Moreover, a similar procedure is used to write the "down" bits. After these are correctly selected, there are several options for the information to be propagated. The electric field that forms the gates can be sequentially controlled (clocked) to propagate the information through the gates to do the appropriate logic functions or sections (or intended memory or storage) of the array can be controlled simultaneously, but the size of these sections must be such that the information will be certain to propagate in the forward direction (semi-autonomous operation). Thus, clocking the array embodiment approach provides the appropriate directionality and the array can be operated at significantly higher speed than if run autonomously or semi- autonomously. Reading

Referring to Figure 7, Figure 7 illustrates that an exemplary approach of reading the bits from the array is to do so capacitively. The nanopillar 5, i.e., ferromagnetic layer (FM), is in communication with the nanopillar layer 11, e.g., a strongly magnetocapacitive material (such as CMC), and there is a large magnetic field on this CMC material from the ferromagnetic (FM) material (i.e., from the nanopillar itself). A global magnetic field 29 is then applied to the array in the "up" direction 12 (specifically shown). The magnetic field in the magnetocapacitive material 11 (e.g., CMC material) will be the sum of the magnetic fields if the moment is in the "up" direction 12 (as illustrated) and the difference of the magnetic fields if the moment is in the "down" direction (not specifically illustrated, but referred to a reference number 13 earlier). Said differently, the capacitance in the CMC is measured using the applied global magnetic field 20 and therefore either adding to or subtracting from the magnetic field produced by the magnetic moment of the FM material. Using the left upper most nanopillar 18 (such as an input bit) as a form of a readout, the capacitance of the nanopillar across the crossbar array will depend on the direction of the magnetization in the nanopillar. This process of reading in the reading phase as, referenced as 21 (e.g., by measuring the capacitance) and the process of writing in the writing phase, as referenced as 20 (by applying the magnetic bias field 19 in the desired or resultant up or down direction, as discussed earlier in Figure 6) can therefore be done with very small magnetic fields (29, 19, respectively). Another method for reading from the logic array can be done magnetoresistively in two ways (not specifically shown in Figure 7). One way of reading magnetoresistively is to use a tunnel junction whose resistance depends on the relative orientation of the nano pillar and the top interconnect which is now made of a magnetic film whose magnetization direction is pinned by an exchange bias layer. The second magnetoresistive method of reading the magnetic logic array is to replace the magnetocapacitive (CMC) 11 layer with a magnetoresistive oxide such as LaSrMnO whose resistance depends strongly on the magnetic field. The reading is done in a manner similar to the magnetocapcitive reading, but through the use of resistance instead of with capacitance as the sensing element. Similar to the previous method, a small global magnetic field is applied in the "up" direction and the total magnetic field seen by the magnetoresistive layer is the sum or difference between the magnetic field of the nanopillar and the applied magnetic field. The sum or difference of the magnetic fields determines the resistance of the magentoresistive layer (i.e., the nanopillar layer) and therefore the output. Logic Gate

Turning to Figure 5(A), a gate pattern could be imposed on an array (such as any array discussed herein) in order to create a logic array such as a NOR gate 17. The gate operation would be initiated by applying an electric field to the uppermost left corner of the input bit 18, which would rotate its magnetization to the "in-plane" direction. A bias magnetic field, such as a very small magnetic field from a small wire loop above the array, can be applied either "up" or "down" as the electric field is removed from the corner nanopillar of the input bit 18, resulting in this bit 18 being written and the gate operating as programmed. As illustrated in Figure 5(A), the input bit 18 constitutes an unwritten or a zero bit (white). Similarly, an output bit 31 may be created using the aforementioned methodology used for the input bit. As illustrated the out bit 31 constitutes a written or one bit (black).

Turning to Figure 5(B), a gate pattern could be imposed on an array (such as any array discussed herein) in order to create a logic array such as a NOT gate 37. The gate operation would be initiated by applying an electric field to the uppermost left corner of the input bit 38, which would rotate its magnetization to the "in-plane" direction. A bias magnetic field, such as a very small magnetic field from a small wire loop above the array, can be applied either "up" or "down" as the electric field is removed from the corner nanopillar of the input bit 38, resulting in this bit 38 being written and the gate operating as programmed. As illustrated in Figure 5(B) the input bit 38 constitutes an unwritten or a zero bit (white). Similarly, an output bit 39 may be created using the aforementioned methodology used for the input bit. As illustrated the out bit 39 constitutes a written or one bit (black).

Moreover, all types are of logic gates are considered part of the present application, such as NAND, OR, XOR, XNOR or AND gates, as well as 2-bit adder, and may, of course, be employed within the context of the invention.

In an embodiment, the gates are written by applying the electric field to those nanopillars in a region that are not part of the gate pattern thus deactivating them. In this case the bits that are not deactivated form the gate array that can perform the logic functions either autonomously or clocked.

These arrays function well as large memory arrays since the bits are non-volatile and can be individually addressed. It is possible to deactivate half of the pillars, or alternate ones, so that the remaining pillars are not coupled to their neighbors and can be individually written with another layers of wires, creating a dual layered device. Using block co-polymer patterning as discussed as a method for creating the middle layer of an array enables the pillar size and spacing to be varied down to the order of about IOnm, respectively, in an embodiment. The pillar size and spacing between the pillars (edge to edge) in an embodiment may be about 5 nm to about 10 nm. Also, it should be appreciated that the pillar size and spacing may be in the range between from about 3 nm to about 25 nm; or less than about 3 nm or greater than about 25 nm.

To manufacture the middle layer of the array there are several methods that can be used. A method is to use block co-polymer patterning. Another method of creating the middle layer of the array is to use electron beam (or e-beam) lithography. This method is a form of maskless lithography in that no mask is required to generate the final pattern. The final pattern for the middle section may be created directly from a digital representation on a computer by controlling an electron beam as it scans across the piezo or electro matrix. Another method of manufacturing the middle layer of the array include using polymer self assembly. This method creates the materials that form the array by embedding them in the polymer and allowing them to precipitate out in a regulated or regular pattern. Another method for constructing the nanopillar middle layer is to use damage template growth of the nanopillars. This method uses focused ion beams to selectively defect the sites for the nanopillars in which they would grow. Figure 10 provides a cross-section of an exploded schematic view of a partial segment of an array pertaining to an embodiment that may use a ferroelectric (FE) material for the nanopillar 5 (rather than a FM material) and a paraelectric material as the nanopillar array layering 11 (rather than the CMC material). The ferroelectric (FE) material of the nanopillar 5, such as for example, BiFeO₃, SrBaTiO₃ PZT, PZN, or any combination thereof, can be deposited so that the polarization could be either up or down and the paraelectric material (for example, BaSrTiO₃ or SrTiO₃) of the nanopillar layering 11 would respond to an electric field during reading in a manner similar to the way the CMC material responds to the global magnetic fields of some of the other embodiments. Regarding the depositing of the ferroelectric (FE) material of the nanopillar 5 whereby it can be deposited so that the polarization could be either up or down, and this being what determines the state of the bit , for example if the nanopillar 5 is polarized up than this could be a "1" and if down a "0". This embodiment is therefore an excellent approach (device, system, and medium) for memory applications. The nanopillars 5 would be located in a matrix 6, which makes up part of the middle layer 4. The matrix may be comprised of FE or PE material, but this is not a requirement as it is for the ferromagnetic (FM) pillars. However, the presence of the FE or PE matrix may facilitate the writing of these pillars (bits) using the electric field. The matrix 6, for example, may be an insulating oxide like SiO₂ or SiN, as well titanium oxide (TiO₂), or other materials as desired or required. A lower substrate 10 or an upper substrate (not shown), or both a lower substrate 10 and an upper substrate may be in communication therewith.

With regards to the reading operation relating to the embodiment of Figure 10, in this case a small electric bias field would have to be applied and the dielectric constant of the paraelectric material of the nanopillar layering 11 would be sensitive to the total electric field due to the ferroelectric material of the nanopillars 5 plus the applied electric field, and again the structure can be read capacitively. The upper wires 2 and lower wires 8 would read out the capacitance using an RF circuit, as well as apply a DC electric field to provide the bias. The wires may accomplish both functions if desired or required, but not necessarily. Some ferroelectric (FE) material ages and so the array could only be written a finite number of times. However, with improved materials engineering of the future and their applications such a limitation would eventually diminish. Such improved materials should be considered part of the present invention and, of course, be employed within the context of the invention. Figure 11 provides a cross-section of an exploded schematic view of a partial segment of an array pertaining to an embodiment that may use a ferromagnetic (FM) material for the nanopillar 5 and a magnetoresistive oxide material (rather than the CMC material as in some of the other embodiments) as the nanopillar array layer 11. The magnetoresistive oxide material is utilized whereby its resistance depends on the magnetic field. The ferromagnetic (FM) material of the nanopillar 5 can be deposited on the bottom layer 7, for example (although not shown, may be deposited on the top layer 1). The nanopillars 5 would be located among a matrix 6, having FE or PE material, which makes up part of the middle layer 4. A lower substrate 10 or an upper substrate (not shown), or both a lower substrate 10 and an upper substrate may be in communication therewith. Regarding the writing operation, similar to some of the other embodiments (e.g., CMC layer) an electric field is applied to the nanopillars and nanopillar layer to put the magnetization and hence the magnetic field in the nanopillar to the "in-plane" direction (i.e., horizontal). A small magnetic bias field is applied in a direction either up or down to accomplish the desired writing. , The magnetoresistive oxide has to be conductive enough so that it can sustain a current whereby resistance can be measured, yet be a poor enough conductor so that both an electric field and a small current can exist simultaneously. In an embodiment, one practice may be to have an additional gate between the nanopillars to provide the electric field if using the same gate for field and current. Again, similar to some of the other embodiments, during the reading operation a global magnetic field (not shown in Figure 11) is applied and the magnetic field at the magnetoresistive oxide nanopillar layer 11 is either the sum or difference of these magnetic fields (i.e., magnetic fields of the FM material of the nanopillars and the applied global magnetic fields), and thereby the resistance of the magnetoresistive oxide material of the nanopillar layer 11 changes with the magnetic field. A current passes through the nanopillars and the nanopillar layer enough so that the resistance can be read by the upper wires 2 and lower wires 8. Therefore the wires are capable of applying the current and reading out the resistance.

EXAMPLES

Practice of an aspect of an embodiment (or embodiments) of the invention will be still more fully understood from the following examples, which are presented herein for illustration only and should not be construed as limiting the invention in any way.

Referring to Figure 9(A), provided is an exemplary approach of implementing or fabricating an embodiment of the Reconfigurable Array Magnetic (RAM) system 171. Two substrates 110, 151 (for example, silicon wafers) are provided and are coated with an insulator layer 103, 109 such as silicon oxide layer of about 100 nm thick (other thicknesses and materials, such as silicon nitride, may be used as desired or required). For example the thickness may be between about 20 nm to about 100 nm; or it may be less than 20 nm or greater than 100 nm. These wafers 110, 151 have embedded in them the transistors 161 and circuits 163 that will provide the voltage to wires that will be embedded in the insulating layer 103, 109. The transistors 161 and circuits 163, such as control circuits will be distributed across the wafers 110, 151 (substrates) and each will be connected to one of the wires in the array at some point using a via (not shown) in the insulator layer 103, 109 of the wafer (substrate) 110, 151. The wires 102, 108 may be embedded in the insulating layer 103, 109 by utilizing a nanoimprint process (or other process approach as desired or required) that exposes the appropriate highly regular wire array on a photoresist mask and deep grooves are formed in the insulator layer 103, 109 using a reactive ion etch specially configured for etching large aspect ratio structures in Si and SiO_2. Alternatively, polymeric methods can be used to form these regular wire arrays. Metal wires 102, 108 (i.e., conductors) are then deposited into the grooves by either chemical, electrochemical or physical deposition methods. These types of processes may further be used other applications for either or both of the wafers 110, 151. For example, these processes may be applied so that each wafer 110, 151 has embedded in them transistors 161 connected to the wires 102, 108 as well as embedded circuits 163, such as control circuits embedded in them and in communication with the transistors and wires. Further, a piezoelectric (PE) or ferroelectric (FE) matrix 106 is deposited on one of the wafers. For the wafer of which the matrix is formed, then that particular wafer may further be processed using a polymeric self assembly approach to deposit the array 125 of magnetic nanopillars 105 embedded in a piezoelectric (PE) or ferroelectric (FE) matrix. An aspect of this process is to insure that the nanopillars are formed over the wires 102, 108 (that exist in the other two wafers 110, 151) in a highly aligned manner. A layer of a colossal magnetocapacitive (CMC) material 111 is deposited uniformly on top of the nanopillar array 125. As illustrated the CMC is deposited over the entire matrix, however it should be appreciated that it may be deposited solely over the nanopillars itself or some combination or variation thereof. The two wafers (of which one will have the array of nanopillars) are flipped chipped together making sure that the wires on the flipped chip wafer run at least substantially perpendicular to the wires in the other wafer and the wires must be aligned with the nanopillars. This sandwich structure will form the RAMA system 151.

Additionally, connections to the RAMA system 151 can be made with contacts 165, such as leads, originating on the periphery of the wafers 110, 151 on the back side (or designated area as desired or required) using vias (not shown) connected to the circuits 163 and/or transistors 161 that will be used to control the RAMA system 151. Also on the back side (or designated area as desired or required) of the wafers 110, 151, a magnetic field source 167 such as provided by helical coils (or other devices as desired or required) can be located on the back surface of the respective substrates. Briefly referring to Figures 9(B)- (C), provided are schematic perspective view of examples of such coils 167. These helical coils on each of the flipped chipped circuits will provide the global magnetic field for writing and reading the array 125. It should be appreciated that this is just one of many ways to form the RAMA system 171 and related circuits but this approach illustrates a pathway to a manufacturable circuit. It should be appreciated that the circuits, transistors, leads, coils and various other supporting elements or interface elements associated with the RAMA system 171 may be located in various locations (embedded, adjacent, surface) and may have any number of components, as well as various sizes, shapes and types as desired or required. Although not shown, the RAMA system 171, may be utilized for and as a part of, and in communication with (by way of the contacts or leads, for example) at least one of the following, but not limited thereto: microprocessors, microcontrollers, static RAM, and other digital logic circuits and memory circuits both embedded with the logic circuits or stand alone. Although not shown, the RAMA system 171, may be utilized for and as a part of, and in communication with (by way of the contacts or leads, for example) with at least one of the following, but not limited thereto: a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for may types of communication. Any possible wireless communication may be applied to or with any of the aforementioned elements discussed herein (rather than hardwire or circuitry).

The following patents, applications and publications as listed below and throughout this document are hereby incorporated by reference in their entirety herein.

The devices, systems, computers, processors, apparatuses, compositions and methods of various embodiments of the invention disclosed herein may utilize aspects disclosed in the following references, applications, publications and patents and which are hereby incorporated by reference herein in their entirety:

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It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, which are intended to define the scope of the invention. Unless clearly specified to the contrary, there is no requirement for any particular described or illustrated activity or element, any particular sequence or such activities, any particular size, speed, material, duration, contour, dimension or frequency, or any particularly interrelationship of such elements. Moreover, any activity can be repeated, any activity can be performed by multiple entities, and/or any element can be duplicated. Further, any activity or element can be excluded, the sequence of activities can vary, and/or the interrelationship of elements can vary. It should be appreciated that aspects of the present invention may have a variety of sizes, contours, shapes, compositions and materials as desired or required. In summary, while the present invention has been described with respect to specific embodiments, many modifications, variations, alterations, substitutions, and equivalents will be apparent to those skilled in the art. The present invention is not to be limited in scope by the specific embodiment described herein. Indeed, various modifications of the present invention, in addition to those described herein, will be apparent to those of skill in the art from the foregoing description and accompanying drawings. Accordingly, the invention is to be considered as limited only by the spirit and scope of the following claims, including all modifications and equivalents.

Still other embodiments will become readily apparent to those skilled in this art from reading the above-recited detailed description and drawings of certain exemplary embodiments. It should be understood that numerous variations, modifications, and additional embodiments are possible, and accordingly, all such variations, modifications, and embodiments are to be regarded as being within the spirit and scope of this application. For example, regardless of the content of any portion (e.g., title, field, background, summary, abstract, drawing figure, etc.) of this application, unless clearly specified to the contrary, there is no requirement for the inclusion in any claim herein or of any application claiming priority hereto of any particular described or illustrated activity or element, any particular sequence of such activities, or any particular interrelationship of such elements. Moreover, any activity can be repeated, any activity can be performed by multiple entities, and/or any element can be duplicated. Further, any activity or element can be excluded, the sequence of activities can vary, and/or the interrelationship of elements can vary. Unless clearly specified to the contrary, there is no requirement for any particular described or illustrated activity or element, any particular sequence or such activities, any particular size, speed, material, dimension or frequency, or any particularly interrelationship of such elements. Accordingly, the descriptions and drawings are to be regarded as illustrative in nature, and not as restrictive. Moreover, when any number or range is described herein, unless clearly stated otherwise, that number or range is approximate. When any range is described herein, unless clearly stated otherwise, that range includes all values therein and all sub ranges therein. Any information in any material (e.g., a United States/foreign patent, United States/foreign patent application, book, article, etc.) that has been incorporated by reference herein, is only incorporated by reference to the extent that no conflict exists between such information and the other statements and drawings set forth herein. In the event of such conflict, including a conflict that would render invalid any claim herein or seeking priority hereto, then any such conflicting information in such incorporated by reference material is specifically not incorporated by reference herein.

Claims

CLAIMSI claim:

1. A non- volatile reconfigurable array of modifiable automata (RAMA) device comprising: an array of nanopillars functionally addressable by conducting elements that provide a control electric field to said nanopillars; and said array of nanopillars comprise at least one material whose properties can be controlled by said control electric field.

2. The device of claim 1 , wherein the nanopillar properties being the direction of magnetization of the material of at least one of said nanopillars of said nanopillar array.

3. The device of claim 2, wherein the material of said nanopillar comprises a ferromagnetic (FM) material.

4. The device of claim 2, wherein the direction of magnetization of at least one nanopillar is a direction that is at least substantially in-plane with said nanopillar array.

5. The device of claim 2, wherein if the direction of magnetization of one of said nanopillars is not in the direction that is at least substantially in-plane with said nanopillar array then respective said nanopillar will not be written.

6. The device of claim 4, wherein said in-plane direction of said at least one nanopillar deactivates respective said at least one nanopillar.

7. The device of claim 6, wherein said at least one nanopillar comprises an oxide material.

8. The device of claim 7, wherein said oxide material comprises a ferromagnetic (FM) material.

9. The device of claim 8, wherein said ferromagnetic (FM) material comprises at last one any of the following materials: CoFeO4, FE3O4, other strongly ferromagnetic oxide or material that is ferromagnetic to temperatures well above ambient temperature and whose unstrained magnetization is parallel with the axis of said nanopillars.

10. The device of claim 7, further comprising a bias magnetic field applied to at least one of said deactivated nanopillars.

11. The device of claim 10, wherein direction of said magnetic bias field determines how said deactivated nanopillar is written.

12. The device of claim 11 , wherein said written nanopillar may be written as a

"0" or a "l."

13. The device of claim 12, wherein a written nanopillar may be for writing at least any one of the following: logic gate, memory, or writing input bits.

14. The device of claim 1, further comprising a layer for said array of nanopillars located above or below said array of nanopillars.

15. The device of claim 14, wherein said nanopillar layer comprises a material whose properties can be controlled by a magnetic bias field.

16. The device of claim 15, wherein said nanopillar layering comprises an oxide material.

17. The device of claim 16, wherein said oxide material comprises a colossal magnetocapacative (CMC) material.

18. The device of claim 17, further comprising a global magnetic field applied to said array of nanopillars in a direction at least substantially parallel to said nanopillars.

19. The device of claim 18, wherein: said conducting elements are adapted to read capacitively, wherein the magnetic field on said oxide material or CMC material of said nanopillar layering is subject to the sum of the fields produced by the magnetic moments of the nanopillars and the applied global magnetic field.

20. The device of claim 19, wherein if the magnetic moments of the nanopillars and the applied global magnetic field are in the same direction then their magnetic fields is greater than if they are in opposite directions thereby providing a difference in magnetic field, wherein the difference in magnetic field is what provides a difference in the dielectric constant of the oxide material and can be sensed capacitively.

21. The device of claim 18, wherein the magnetic field on said oxide material of said nanopillar layering is subject to the sum of the fields produced by the magnetic moments of the nanopillars and the applied global magnetic field, and wherein said conductors read the capacitance of the dielectric constant of the oxide material.

22. The device of claim 15, wherein said nanopillar layering comprises a magnetoresistive material.

23. The device of claim 22, wherein said magnetoresistive oxide material comprises LaSrMnO material or other suitable material.

24. The device of claim 23, further comprising a global magnetic field applied to said array of nanopillars in a direction at least substantially parallel to said nanopillars.

25. The device of claim 24, wherein: said conducting elements are adapted to read resistively, wherein the magnetic field on said magnetoresistive oxide material of said nanopillar layering is subject to the sum of the fields produced by the magnetic moments of the nanopillars and the applied global magnetic field.

26. The device of claim 25, wherein: said conducting elements are adapted to read resistively, wherein the resistance of the magnetoresistive oxide material of the nanopillar layer changes with the magnetic field.

27. The device of claim 24, wherein said conducting elements are adapted for applying a current.

28. The device of claim 1 , wherein said device is a logic device or memory device.

29. The device of claim 1 , wherein said device is a logic device and memory device combined.

30. The device of claim 1, further comprising a nanopillar layer in communication with said array of nanopillars, and wherein: said conducting elements comprise first conducting elements in communication with said nanopillar layering; said conducting elements comprise second conducting elements in communication with said nanopillars; and wherein said first and second conducting elements provide an electric filed across said nanopillars.

31. The device of claim 1 , wherein said array of nanopillars are embedded in a ferroelectric (FE) or piezoelectric (PE) matrix.

32. The device of claim 1, wherein said first conducting elements are disposed directly or indirectly with a substrate distal from said second conducting elements.

33. The device of claim 32, wherein said second conducting elements are disposed directly or indirectly with a second substrate distal from said first conducting elements.

34. The device of claim 1, wherein said second conducting elements are disposed directly or indirectly with a substrate distal from said first conducting elements.

35. A method for constructing the device of any one of claims 32, 33 or 34, wherein said array of nanopillars are constructed with at least one of the following methods: applying brute force lithography patterning to said substrate or said second substrate; applying lithography patterning to said substrate or said second substrate; or applying e-bean lithography patterning to said substrate or said second substrate.

36. The method of claim 35, wherein said nanopillars may be multilayered or single layered with perpendicular anistrophy in the unstrained condition.

37. A method for constructing the device of any one of claims 32, 33 or 34, wherein said array of nanopillars are constructed with at least one of the following methods: applying block co-polymer patterning to said substrate or said second substrate; or applying polymeric self-assembly to said substrate or said second substrate.

38. The method of claim 37, wherein materials that form said nanopillars are embedded in the polymer and precipitate out in a regular pattern.

39. A method for constructing the device of any one of claims 32, 33 or 34, wherein said array of nanopillars are constructed with the following methods: applying damage template growth patterning to said substrate or said second substrate.

40. The method of claim 39, wherein said nano-pillars may be multilayered or single layered with perpendicular anistrophy in the unstrained condition.

41. The device of claim 1 , further comprising: said first conducting elements are aligned substantially laterally and top insulating material is disposed between said first conducting elements to provide a first layer; said second conducting elements are aligned substantially longitudinally and bottom insulating material is disposed between said second conducting elements top provide a second layer; said array of nano pillars and said nanopillar layering are disposed between said first layer and said second layer to provide a middle layer.

42. The device of claim 41 , wherein a portion of said top insulating material or portion of said bottom second insulating layer or both said top insulating material or said bottom insulating layer acts as a tunnel barrier.

43. The device of claim 1, wherein said nanopillars are embedded in a ferroelectric (FE) or piezoelectric (PE) matrix.

44. The device of claim 1 , wherein at least four of said nanopillars provide a bit.

45. The device of claim 44, wherein said bit comprises a square with two corners polarized up and two corners polarized down.

46. The device of claim 1 , wherein at least two of said nanopillars provide a bit.

47. The device of claim 1 , wherein one of said nanopillars provide a bit.

48. The device of claim 1, wherein at least nine of said ferromagnetic nanopillars provide a bit.

49. A method for reading from said logic array or memory array of claim 1 , wherein said method comprises: performing said reading magnetoresistively by using a tunnel junction whose resistance depends on the relative orientation of said nanopillars and its top interconnect portion, wherein said interconnect portion is made of a magnetic film whose magnetization direction is pinned by an exchange bias layer.

50. A method for reading from said logic array or memory array of claim 1 , wherein said method comprises: providing nanopillar layer in communication with said nanopillars, comprising a magnetoresistive oxide material; and performing said reading magnetoresistively of said magnetoresistive oxide whose resistance material depends strongly on magnetic field.

51. The device of claim 1 , wherein said array of nanopillars comprise a ferromagnetic (FM) materials.

52. The device of claim 51 , wherein said ferromagnetic nanopillars are arranged antiferromagentically with one another.

53. The device of claim 52, wherein said antiferromagnetic arrangement comprising arranging said nanopillars in groups of at least two whereby their magnetic field is zero when there is no electric field applied.

54. The array of claim 53, wherein said ferromagnetic nanopillar array provides a logic array or memory array, or both a logic array or memory array.

55. The device of claim 51 , wherein said nanopillar array provides a logic array or memory array, or both a logic array or memory array.

56. The device of claim 55, wherein at least four of said ferromagnetic nanopillars provide a bit.

57. A method for initiating a gate operation of said logic array or operation of a memory array of claim 56, by applying an electric field to a location of said bit for rotating its magnetization in plane.

58. The method of claim 57, wherein said location is a corner.

59. The method of claim 57, wherein said gate operation comprises at least one of the following gates: NOR, NOT, NAND, OR, AND, XOR, XNOR, 2-bit adder, or any combination thereof.

60. A method for writing to said logic array of claim 55, in which a small magnetic field from adjacent to said logic array or operation of a memory array is applied in either an up direction, down direction or any combination of directions while the applied electric field is removed.

61. A method for writing to said logic array of claim 55, wherein said method comprises: deactivating all of said nanopillars that are intended to be input nanopillars; applying a small bias magnetic field to said logic array in a positive direction; selectively activating gates; and simultaneously turning off the field and the gates and allowing the information to propagate.

62. A method for writing to said logic array of claim 55, wherein said method comprises: deactivating all of said nanopillars that are intended to be input nanopillars; applying a small bias magnetic field to said logic array in a positive direction; selectively activating gates; and turning off the field and clocking the removal of the gate voltages of said logic array, driving the propagation of the information at the clocking field.

63. The device of 51 , further comprising a nanopillar layer in communication with said nanopillars.

64. The device of claim 63, wherein said nanopillar layering comprises an oxide material.

65. The device of claim 64, wherein said oxide material comprises a colossal magnetocapacative (CMC) material, exhibiting very large changes of dielectric constant with the applied magnetic field.

66. The device of claim 65, wherein said magnetocapacative (CMC) material comprises at least one of the following material: LaPrCaMnO₃, LaSrMnO₃ other manganite, or any combination thereof.

67. A method for reading from said logic array or operation of a memory array of claim 64, wherein said method comprises: performing said reading capacatively by applying a global magnetic field to said logic array or memory array in a direction parallel to said nano pillars and wherein the field on said oxide material of said nanopillar layering is subject to the sum of the fields produced by the magnetic moments of the nanopillars and the applied global magnetic field.

68. The method of claim 67, wherein if the magnetic moments of the nanopillars and the applied global magnetic field are in the same direction is greater than if they are in opposite direction thereby providing a difference in magnetic field, wherein the difference in magnetic field is what provides a difference in the dielectric constant of the oxide material and can be sensed capacitively.

69. The method of claim 68, wherein first conductors and second conductors are provided, and capacitance is read out between said first conductors and said second conductors.

70. The method of claim 67, wherein said oxide material comprises a colossal magnetocapacative (CMC) material.

71. The method of claim 67, wherein said nanopillar layer comprises a colossal magnetocapacitive (CMC) material.

72. The device of claim 51 , wherein said nano pillars are embedded in a ferroelectric (FE) or piezoelectric (PE) matrix.

73. The device of claim 72, wherein said ferroelectric (FE) or piezoelectric (PE) matrix comprises at least on of the following materials: BiFeO3, SrTiO₃, SrBaTiO₃ PZT, PZN, or any combination thereof.

74. The device of claim 51 , wherein said ferromagnetic (FM) material comprises at least one of the following materials: CoFeO4, FE3O4, other strongly ferromagnetic oxide or material that is ferromagnetic to temperatures well above ambient temperature and whose unstrained magnetization is parallel with the axis of said nanopillars.

75. The device of claim 1 , wherein the nanopillar properties being the direction of polarization of at least one of said nanopillars of said nanopillar array.

76. The device of claim 75, wherein the material of said nanopillar comprises a ferroelectric (FE) material.

77. The device of claim 75, wherein the direction of polarization of at least one nanopillar is a direction that is either up or down.

78. The device of claim 77, wherein the up or down direction is at least substantially in plane with the axis of said at least one nanopillar.

79. The device of claim 75, wherein if the direction of polarization of one of said nanopillars is not in the up or down direction then respective said nanopillar will not be written.

80. The device of claim 79, wherein said direction of said at least one nanopillar that is not up or down, then said nanopillar is deactivated.

81. The device of claim 80, wherein said nanopillar layer comprising a paraelectric material.

82. The device of claim 81 , wherein said paraelectric material comprises at least one Of SrTiO₃ or BaSrTiO₃.

83. The device of claim 75, wherein said nano pillars are embedded in a ferroelectric (FE) or piezoelectric (PE) matrix.

84. The device of claim 75, wherein said nano pillars are embedded in an insulating oxide

85. The device of claim 84, wherein said insulating oxide comprises at least one of the following: SiO₂ or SiN, TiO₂, or any combination thereof.

86. The device of claim 75, wherein said direction of the polarization determines how said at least one nanopillar is written.

87. The device of claim 86, wherein said up or down direction determines how said at least one nanopillar is written.

88. The device of claim 86, wherein said written nanopillar may be written as a "0" or a "l."

89. The device of claim 86, wherein a written nanopillar may be for writing memory.

90. The device of claim 86, further comprising a nanopillar layer for said array of nanopillars located above or below said array of nanopillars.

91. The device of claim 90, wherein said nanopillar layer comprises a material whose properties can be controlled by an electric bias field.

92. The device of claim 90, wherein said nanopillar layer comprises a paraelectric (PE) material.

93. The device of claim 92, wherein said paraelectric material comprises at least any one Of BaSrTiO₃ or SrTiO₃, or any combination thereof.

94. The device of claim 92, wherein properties of nanopillar layer is effected by said electric bias field by effecting the dielectric constant of said nanopillar layer.

95. The RAMA device of claim 1, wherein said RAMA device is in communication with at least one of any of the following application devices: microprocessors, microcontrollers, static RAM, and other digital logic circuits and memory circuits.

96. The RAMA device of claim 95, wherein said communication includes being interfaced therewith said application device.

97. The RAMA device of claim 95, wherein said communication includes being integral with and as component of said application device.

98. The RAMA device of claim 1 , wherein said RAMA device is used with or embedded in at least one of any of the following application devices: microprocessors, microcontrollers, static RAM, and other digital logic circuits and memory circuits.

99. The RAMA device of claim 1, wherein said RAMA device is in communication with at least one of any of the following application devices: analog circuits, such as image sensors, data converters, and highly integrated transceivers.

100. The RAMA device of claim 99, wherein said communication includes being interfaced therewith said application device.

101. The RAMA device of claim 99, wherein said communication includes being integral with and as component of said application device.

102. The RAMA device of claim 1, wherein said RAMA device is used with or embedded in at least one of any of the following application devices: analog circuits, such as image sensors, data converters, and highly integrated transceivers.

103. A device comprising a non- volatile array of magnetic nanopillars, wherein said nanopillars being previously written at some prior time, said device comprises: said nanopillar comprises a ferromagnetic (FM) material; a layer for said array of nanopillars located above or below said array of nanopillars, said nanopillar layer comprises a colossal magnetocapacative (CMC) material; and if a global magnetic field is applied to said array of nanopillars in a direction at least substantially parallel to said nanopillars, then: the magnetic field on said CMC material of said nanopillar layering is subject to the sum of the fields produced by the magnetic moments of the nanopillars and the applied global magnetic field, and wherein said capacitance of the dielectric constant of the CMC material is capable of being read.

104. The device of 103, wherein said written nanopillars comprising at least one of the following: 1 's and O's or information.

105. A device comprising a non- volatile array of magnetic nanopillars, wherein said nanopillars being previously written at some prior time, said device comprises: said nanopillar comprises a ferromagnetic (FM) material; a layer for said array of nanopillars located above or below said array of nanopillars, said nanopillar layer comprises a magnetoresistive oxide material; and if a global magnetic field is applied to said array of nanopillars in a direction at least substantially parallel to said nanopillars, and current is passed through said nanopillars and said nanopillar layer, then: the resistance on said magnetoresistive oxide material of said nanopillar layering changes, and wherein said resistance of the magnetoresistive oxide material is capable of being read.

106. The device of 105, wherein said written nanopillars comprising at least one of the following: 1 's and O's or information.

107. A device comprising a non-volatile array of magnetic nanopillars, wherein said nanopillars being previously written at some prior time, said device comprises: said nanopillar comprises a ferroelectric (FE) material; a layer for said array of nanopillars located above or below said array of nanopillars, said nanopillar layer comprises a paraelectric material; and if an electric field is applied to said nanopillars, then: the electric field on said paraelectric material of said nanopillar layering is sensitive to the total electric field due to the ferroelectric (FE) material of said nanopillars and the applied electric field, and wherein said capacitance of the dielectric constant of the paraelectric material is capable of being read.

108. The device of 107, wherein said written nanopillars comprising at least one of the following: 1 's and O's or information.